The present invention relates to amplifiers for use in integrated circuits and, particularly, to techniques for canceling offset voltages in such amplifiers.
For an ideal amplifier, when the differential input voltage is zero, the output voltage is also zero. In reality, however, the output voltage may not be zero because of device mismatches among circuit components. This offset can be expressed by an input offset voltage, which typically refers to the required input voltage to an amplifier such that the amplifier's output voltage is zero.
An offset can be caused by mismatches due to uncertainties in the device manufacturing process, such as transistor dimensions and doping levels. The presence of an offset limits the performance of an amplifier because the amplifier's output contains not only the amplified input signal, but also the amplified input offset voltage. This can be problematic in precision circuits that demand high accuracy, or when multiple amplifier channels must match one another, since mismatches are generally random and uncorrelated.
A technique, called “ping-ponging,” is sometimes used to increase throughput in an amplifier signal chain. If an amplifier requires two separate phases (e.g. reset and amplify), this technique allows two amplifiers to operate out of phase with one another on the same signal path. In other words, while one amplifier is resetting, the other is amplifying, and vice versa. In this way, one of the amplifiers is always amplifying and there is no time wasted on the reset operation.
Unfortunately, differences in amplifier offsets can produce a major challenge to the use of ping-ponging in many applications. For example, if ping-ponging is used in an image sensor readout circuit and the two amplifiers have different offset voltages, the technique can generate fixed patterns in the image, where even and odd columns have different offsets with respect to one another. The human eye is sensitive to image artifacts such as these, making them undesirable. Robust auto-zero techniques can be used to remove these offsets and eliminate such effects.
Known auto-zero circuits often apply a two-phase operation to cancel the amplifier offset. In the “acquisition” phase, the amplifier's inputs may be shorted together and a representation of the offset acquired by auto-zero capacitors. In the “hold” phase, the capacitors hold the acquired voltages, which may be applied to the circuit such that the represented offset voltage is subtracted from the inherent amplifier offset. One common issue for the known auto-zero circuits is the introduction of additional sampling noise on the auto-zero capacitors. Although the sampling noise can generally be reduced by increasing the capacitance of the capacitors, this approach can be impractical in high-speed systems because it negatively affects the acquisition bandwidth during the acquisition phase.
FIG. 1 illustrates an auto-zero circuit for an amplifier 100 according to the prior art. The amplifier 100 includes a pair transconductance amplifiers 110, 120 with respective transconductances Gm1 and Gm2, auto-zero capacitors C1.1, C1.2, and control switches SW1.1, SW1.2, SW2.1 and SW2.2. For purposes of this discussion it is assumed that Gm1 and Gm2 are derived from metal-oxide-semiconductor field-effect transistors (MOSFETs) with transconductances of gm1 and gm2, respectively.
The auto-zero circuit operates in two phases—an acquisition phase and a hold phase. In the acquisition phase, switches SW1.1, SW1.2, SW2.1 and SW2.2 are closed, which connects a common-mode voltage VCM to the inputs of the first amplifier 110. Any input offset voltage may produce a differential current at the output of the first transconductance amplifier 110, which is applied to the output of the second transconductance amplifier 120 in feedback and produces a differential voltage ΔV equal to VOS(gm1/gm2) where VOS is the input-referred offset. The voltages at internal nodes VAZ1 and VAZ2 and, therefore, this differential voltage ΔV are acquired by auto-zero capacitors C1.1 and C2.1, respectively.
Because the inputs and the outputs of the transconductance amplifier 120 are shorted by the switches SW1.1 and SW1.2, the bandwidth in the acquisition phase, called the “acquisition bandwidth,” is given by:
                    BW        =                              g                          m              ⁢                                                          ⁢              2                                            2            ⁢            π            ⁢                                                  ⁢                          C              1                                                          Eq        .                                  ⁢                  (          1          )                    where C1 represents the capacitance of each of the auto-zero capacitors C1.1 and C1.2.
Acquisition bandwidth and settling time of the auto-zero capacitors are inversely proportional to one another. More specifically, eq. (1) can be expressed as BW=1/2πτ where the time constant τ=C1/gm2. Furthermore, settling time can be expressed as the number of time constants required to achieve a required settling accuracy, which can be derived from a required auto-zeroing accuracy. For example, in order for the capacitors to settle to 99.3% of their final value requires an acquisition time of approximately 5 time constants or 5τ. If the bandwidth is less than 1/2πτ, the capacitors may not fully settle, resulting in incomplete offset cancellation.
In the hold phase, switches SW1.1, SW1.2, SW2.1 and SW2.2 may be opened. The auto-zero capacitors C1.1 and C1.2 hold the voltages across them at the end of the acquisition phase and, therefore, transconductance amplifier 120 may produce an amount of current to cancel the offset produced during the acquisition phase. In this way, the output-referred offset voltage between the output nodes Vout1 and Vout2 should be cancelled and the amplifier 100 should amplify only the differential input voltage presented to it at inputs VIN1 and VIN2.
Use of the auto-zero circuit depicted in FIG. 1 may introduce additional noise components because the auto-zero capacitors C1.1 and C2.1 sample noise of the circuit in addition to the offset. However, since noise is a random signal, its instantaneous value is non-deterministic and likely will not be cancelled during the hold phase as the offset is. Nevertheless, the circuit 100 may find application in scenarios where the increase of random noise is acceptable relative to the cancellation of correlated noise.
Moreover, it can be shown that the input-referred auto-zero noise introduced by the sampling operation may be given by:
                                                                        N                i                            =                                                                                                                  S                        ⁡                                                  (                          f                          )                                                                    ·                      Δ                                        ⁢                                                                                  ⁢                    f                                                        g                                          m                      ⁢                                                                                          ⁢                      1                                        2                                                                                                                          =                                                                                          [                                              2                        ⁢                                                  (                                                                                                                    8                                ⁢                                                                                                                                  ⁢                                kT                                                            3                                                        ⁢                                                          (                                                                                                g                                                                      m                                    ⁢                                                                                                                                                  ⁢                                    1                                                                                                  +                                                                  g                                                                      m                                    ⁢                                                                                                                                                  ⁢                                    2                                                                                                                              )                                                                                )                                                                    ]                                        ⁡                                          [                                                                        g                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                                                    4                          ⁢                                                                                                          ⁢                                                      C                            1                                                                                              ]                                                                            g                                          m                      ⁢                                                                                          ⁢                      1                                        2                                                                                                                          =                                                1                                      g                                          m                      ⁢                                                                                          ⁢                      1                                                                      ⁢                                                                                                    4                        ⁢                                                                                                  ⁢                        kT                                                                    3                        ⁢                                                                                                  ⁢                                                  C                          1                                                                                      ⁢                                          (                                                                        g                                                      m                            ⁢                                                                                                                  ⁢                            1                                                                          +                                                  g                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                                              )                                        ⁢                                          g                                              m                        ⁢                                                                                                  ⁢                        2                                                                                                                                                    Eq        .                                  ⁢                  (          2          )                    where Ni is the input-referred auto-zero noise, S(f) is the noise spectral density, and Δf is the noise bandwidth.
As previously discussed, the acquisition bandwidth is gm2/(2πC1), and determines the settling time of the auto-zero capacitors. Therefore, it may be difficult to simultaneously achieve acceptable input-referred auto-zero noise and fast enough settling for a given application. For example, in order to lower input-referred auto-zero noise, it is desirable to reduce gm2. However, reducing gm2 may lower the acquisition bandwidth and increase settling time. Similarly, increasing C1 lowers the input-referred auto-zero noise, but may lower the acquisition bandwidth, also leading to increased settling time.
As noted, these designs can suffer from a tradeoff between cycle-to-cycle sampling noise and acquisition bandwidth. Accordingly, there is a need in the art for an auto-zero amplifier circuit that can maintain a high acquisition bandwidth with reduced sampling noise.